1. Field of the Invention
This invention relates to a new type of data processing system. More particularly, it relates to a data processing system in which operations are carried out through use of a number system allowing data processing operations to be carried out more efficiently than with a conventional constant radix number system. Most especially, it relates to such a data processing system in which operations involving large numbers may be carried out in a substantially simpler manner than with conventional data processing systems.
2. Description of the Prior Art
There are a variety of data processing systems and sub-systems known in the prior art which perform arithmetical operations using the so-called system of residual classes or residue class arithmetic. In such systems, prime or relatively prime or mutually prime radices are employed. Relatively prime or mutually prime radices have no common divisor, even though the individual radices may be divisible by other than one and the radix itself. Examples of such systems and sub-systems are disclosed in U.S. Pat. No. 3,167,645; U.S. Pat. No. 3,602,704; U.S. Pat. No. 3,980,874; U.S. Pat. No. 4,041,084; and U.S. Pat. No. 4,064,400. However, such prior art systems employ the Chinese Remainder Theorem, which requires the storage and use of a large number of constants, to convert the modular numbers used to perform calculations in the system back into decimal or binary form for output. For example, "Modular Arithmetic . . . an Ancient Science for a New Computer", Westinghouse Engineer, July 1963, pp. 112-114, points out that such a reconversion for a system using the prime numbers 2 through 31 would require storage of 150 predetermined constants of about 40 bits each, or a total of 6,000 bits.
There are also scientifically oriented data processing systems which are capable of carrying out certain types of calculations substantially faster than typical general purpose data processing systems. For example, one such system operates at 80,000 operations per second and multiplies one decimal digit at a time. With a 64-bit data bus it can handle 8 decimal digits to a 16 digit product without using a multiple precision routine. This involves 64 machine cycles for the multiplications and 64 machine cycles for the additions, or a minimum of 128 machine cycles per 8 digit number.